Methods and apparatus to reduce switching losses in power converters

ABSTRACT

Methods, apparatus, systems and articles of manufacture are disclosed to reduce switching losses occurring in power converters. An example a converter including an input voltage node and an output voltage node, a controller coupled to the converter, and a compensation network coupled to the converter and to the controller, the compensation network adapted to conduct a current to the converter in response monitoring a first voltage at the input voltage node being a threshold difference than a second voltage at the output voltage node.

FIELD OF THE DISCLOSURE

This disclosure relates generally to power converters, and, moreparticularly, to methods and apparatus to reduce switching losses inpower converters.

BACKGROUND

A power converter is a circuit used in various electrical systems toconvert an input voltage to a desired output voltage. For example, aboost converter converts an input voltage into a higher output voltageby controlling transistors and/or switches to charge and/or dischargeinductors and/or capacitors to maintain the desired output voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic illustration of a boost converter system.

FIGS. 2A-2C are plots of the voltage across the switching device of FIG.1 versus time and the current conducting though the inductor of FIG. 1versus time, at various input voltage levels.

FIG. 3 is a schematic illustration of an example boost converter systemcoupled to an example compensation network to reduce switching loss inthe boost converter system.

FIG. 4 is a plot of various voltage, current, and enable signals versustime in the boost converter system of FIG. 3.

FIG. 5 is a plot of the current conducting through the switching deviceof FIG. 3 versus time during quasi-resonant operation.

FIGS. 6A-6B are plots of various voltage and current signals of theswitching device of FIG. 3, shown on a more focused timescale than theplot in FIG. 5.

FIG. 7 is a plot of the current conducting through the switching deviceof FIG. 3 versus time for zero voltage switching operation.

FIGS. 8A-8B are plots of various voltage and current signals of theswitching device of FIG. 3, shown on a more focused timescale than theplot in FIG. 7.

FIG. 9 is a plot of current conducting through the inductor of FIG. 3versus time and a frequency domain representation of the currentconducting through the inductor of FIG. 3.

FIG. 10 is a schematic illustration of an example buck converter systemcoupled to an example compensation network to reduce switching loss inthe buck converter system.

FIG. 11 is a schematic illustration of an example buck-boost convertersystem coupled to an example compensation network to reduce switchingloss in the buck-boost converter system.

FIG. 12 is a flowchart representative of a process that may beimplemented using logic or machine readable instructions that may beexecuted to implement the compensation network of FIG. 3, thecompensation network of FIG. 10, or the compensation network of FIG. 11,to reduce switching losses occurring in the boost converter system, thebuck converter system, or the buck-boost converter system.

The figures are not to scale. In general, the same reference numberswill be used throughout the drawing(s) and accompanying writtendescription to refer to the same or like parts

Descriptors “first,” “second,” “third,” etc. are used herein whenidentifying multiple elements or components that may be referred toseparately. Unless otherwise specified or understood based on theircontext of use, such descriptors are not intended to impute any meaningof priority, physical order or arrangement in a list, or ordering intime but are merely used as labels for referring to multiple elements orcomponents separately for ease of understanding the disclosed examples.In some examples, the descriptor “first” may be used to refer to anelement in the detailed description, while the same element may bereferred to in a claim with a different descriptor such as “second” or“third.” In such instances, it should be understood that suchdescriptors are used merely for ease of referencing multiple elements orcomponents. Connection references (e.g., attached, coupled, connected,and joined) are to be construed broadly and may include intermediatemembers between a collection of elements and relative movement betweenelements unless otherwise indicated. As such, connection references donot necessarily infer that two elements are directly connected and infixed relation to each other.

DETAILED DESCRIPTION

A boost converter system is a circuit including an inductor, acapacitor, a switching device (e.g., metal oxide semiconductor fieldeffect transistors (MOSFETs), etc.), and a diode configured to generatea desired output voltage from an input voltage. A controller of theboost converter system enables or disables conduction of a switchingdevice in order to regulate the output voltage of the boost convertersystem. The boost converter system generates a desired output voltagefrom the input voltage based on the controller enabling or disablingconduction of the switching device. For example, the controller of aboost converter system may enable the switching device (e.g., a MOSFET),thereby current to conduct from the power source, through the inductorto ground. As such, enabling the switching device will cause current toflow through the inductor, thereby storing energy in a magnetic field ofthe inductor coil. Once the inductor is sufficiently charged, thecontroller disables conduction of the switching device and the currentfrom the inductor flows to the capacitor and the load, while thecapacitor maintains the desired output voltage of the boost converterand the load receives power. The switching pattern noted above allowsfor current to flow into the load of a boost converter system. Thecontroller toggles the switching control to ensure that boost converterconverts the input voltage to a higher, desired output voltage.

FIG. 1 is a schematic illustration of a boost converter system 100. Theboost converter system 100 includes an inductor 102, a capacitor 104, aswitching device 106, a diode 108, a load 110, a switch capacitance 112,a voltage source 114, and a controller 116. As described above, thecontroller 116 enables and disables the switching device 106 to controlcurrent conducting though the boost converter system 100. In FIG. 1,switching loss of the boost converter system 100 may be based on thevoltage across the switching device 106 when the switching device 106 isenabled.

The boost converter system 100 is operable in various modes:discontinuous conduction mode (DCM), continuous conduction mode (CCM),and/or transition mode (TM). If the boost converter system 100 operatesin DCM, the controller 116 generates and/or otherwise provides theenable signal (line 101) to the switching device 106 when the currentconducting though the inductor 102 is zero amperes for a finite periodof time (e.g., zero amperes for 0.2 seconds, 0.6 seconds, or anysuitable threshold of time).

If the boost converter system 100 operates in CCM, the controller 116generates and/or otherwise provides the enable signal (line 101) to theswitching device 106 when the current conducting though the inductor 102is slightly greater than, or at, a lower current limit. For example, ifthe lower current limit is 1 ampere, the controller 116 provides and/orotherwise generates the enable signal (line 101) when the currentconducting though the inductor discharges to, or is slightly above(e.g., microamperes above, etc,), 1 ampere.

If the boost converter system 100 operates in TM, the controller 116generates and/or otherwise provides the enable signal (line 101) to theswitching device 106 the moment the controller 116 determines that thecurrent conducting though the inductor 102 is zero amperes. In TMoperation, the controller 116 may generate and/or otherwise provide theenable signal (line 101) after a negligible delay (e.g., onemicrosecond) in response to determining that the currenting conductingthough the inductor 102 is zero amperes. Likewise, for applicationsincluding the controller operating in TM, the controller 116 maygenerate and/or otherwise provide the enable signal (line 101) to theswitching device 106 in response to determining that the voltage acrossthe inductor 102 and/or switching device 106 is zero volts. In suchapplications, the controller 116 may be referred to as operating as afull zero-voltage switching (ZVS) controller.

A first characteristic of the boost converter system 100 when thecontroller 116 operates as a full ZVS controller is that the voltageacross the switch capacitance 112 rings to zero volts if the inputvoltage is lower than half the output voltage. As such, the lower peakamplitude (e.g., trough or valley) of the voltage across the switchingdevice 106 also rings to zero volts (e.g., because the voltage acrossthe switch capacitance 112 is proportional to the voltage across theswitching device 106). When the controller 116, operating as a full ZVScontroller, monitors zero volts across the switching device 106, thecontroller 116 generates the enable signal (line 101) and, therefore,the switching device 106 may be enabled with a zero-voltage potentialacross the switching device 106.

Alternatively, the controller 116 does not operate as a full ZVScontroller if the input voltage is greater than half the output voltage.As such, the lower peak amplitude (e.g., trough or valley) of thevoltage across the switching device 106 rings to a non-zero voltage(e.g., because the voltage across the switch capacitance 112 is equal tothe voltage across the switching device 106). When the controller 116monitors that the lower peak amplitude of the voltage across theswitching device 106 rings to a non-zero voltage, the controller 116 nolonger operates as a full ZVS controller. As such, the controller 116generates the enable signal (line 101) for the switching device 106 witha non-zero voltage potential across the switching device 106.

FIGS. 2A-2B represents voltage and current signals in the boostconverter system 100 during the first characteristic scenario (e.g.,when the magnitude of the input voltage is lower than half the magnitudeof the output voltage). FIG. 2C represents voltage and current signalsin the boost converter system 100 when the magnitude of the inputvoltage is greater than half the magnitude of the output voltage.

FIGS. 2A-2C are plots 202, 212, 222 of the voltage across the switchingdevice 106 of FIG. 1 versus time and the current conducting though theinductor 102 of FIG. 1 versus time, at various input voltage levels. Inthe plot 202 of FIG. 2A, the input voltage of the boost converter system100 is 75 volts and the output voltage of the boost converter system 100is 390 volts. At a first time interval 204, the inductor current signal(line 206) reaches 0 amperes and, because the input voltage is less thanhalf the output voltage (e.g., 75 volts is less than 195 volts), theswitching device voltage signal (line 208) rings to a lower peakamplitude of zero volts. As such, at a second time interval 210, thevoltage across the switching device 106 (e.g., the magnitude of theswitching device voltage signal (line 208)) reaches zero volts. In FIG.2A, the controller 116 operates as a full ZVS controller.

In the plot 212 of FIG. 2B, the input voltage of the boost convertersystem 100 is 190 volts and the output voltage of the boost convertersystem 100 is 390 volts. At a third time interval 214, the inductorcurrent signal (line 216) reaches 0 amperes and, because the inputvoltage is less than half the output voltage (e.g., 190 volts is lessthan 195 volts), the switching device voltage signal (line 218) rings toa lower peak amplitude of zero volts. As such, at a fourth time interval220, the voltage across the switching device 106 (e.g., the magnitude ofthe switching device voltage signal (line 218)) rings to a lower peakamplitude of zero volts. In FIG. 2B, the controller 116 operates as afull ZVS controller.

In the plot 222 of FIG. 2C, the input voltage of the boost convertersystem 100 is 350 volts and the output voltage of the boost convertersystem 100 is 390 volts. At a fifth time interval 224, the inductorcurrent signal (line 226) reaches 0 amperes and, because the inputvoltage is greater than half the output voltage (e.g., 350 volts isgreater than 195 volts), the switching device voltage signal (line 228)does not ring to a lower peak amplitude of zero volts. As such, at asixth time interval 230, the voltage across the switching device 106(e.g., the magnitude of the switching device voltage signal (line 228))does not ring to a lower peak amplitude of zero volts. Because thevoltage across the switching device 106 (e.g., the magnitude of theswitching device voltage signal (line 228)) does not ring to a lowerpeak amplitude of zero volts, switching losses are increased and thepower density of the boost converter system 100 is reduced.

As such, the boost converter system 100 may operate inefficiently (e.g.,experiences low-power density and high switching loss) when the inputvoltage is greater than half of the output voltage. During conditions inwhich the voltage across the switching device 106 does not ring to alower peak amplitude of zero volts (e.g., because the input voltage isgreater than half the output voltage), the controller 116 operates basedon the quasi-resonant operation of the boost converter system 100 togenerate and/or otherwise provide the enable signal (line 101) at thevalley (e.g., lower limit) of the voltage across the switching device106. During such conditions, the voltage across the switch capacitance112 does not ring to a lower peak amplitude of zero volts and therefore,the voltage across the switching device 106 will not reach zero volts.Because the voltage across the switching device 106 does not ring to alower peak amplitude of zero volts, the switching device 106 is enabledwhen there is a large (e.g., greater than zero) voltage across theswitching device 106. As a result, for a period of time (e.g., 5milliseconds) the switching device 106 experiences a large voltage drop(e.g., greater than zero volts) between the respective drain and sourceterminals of the switching device 106. The large voltage drop (e.g.,greater than zero volts) across the switching device 106 thereby causesswitching losses (e.g., power losses dissipated in the form of heat)occurring in the boost converter system 100. As a result, the boostconverter system 100 experiences inefficient operation in the form of areduction in power density, undesirable switching frequencies, etc.

Examples disclosed herein reduce switching losses in a boost convertersystem. Examples disclosed herein may be utilized in boost convertersystems when the input voltage to the boost converter system is greaterthan half the output voltage of the boost converter system. Additionallyor alternatively, examples disclosed herein may reduce residualswitching losses in any suitable converter such as a buck converter,buck-boost converter, etc.

Examples disclosed herein determine the relationship between the inputvoltage signal and the output voltage signal. In examples disclosedherein, if the input voltage is greater than half the output voltage,the disclosed methods, apparatus, and/or articles of manufacture mayprovide a current to conduct though the inductor to the input voltagesource of a boost converter system. Examples disclosed herein utilize aswitch (e.g., a MOSFET) to conduct, though respective current terminals(e.g., from a drain terminal to a source terminal in a MOSFET), acurrent through the inductor. Such a current may conduct through theinductor for a period of time determined by the controller. In examplesdisclosed herein, the current conducting through the inductor of theboost converter system allows the corresponding voltage across arespective switch capacitance, and across a respective switching device,to decrease, or substantially decrease to, zero volts (e.g., decrease tozero volts, decrease to 1 millivolt, decrease to 2 volts). In anotherexample disclosed herein, the switch may be enabled (e.g., a turn onsignal sent to the switch) when there is a zero-voltage drop across therespective current terminal (e.g., a zero-voltage drop from the drainterminal to the source terminal in a MOSFET).

Examples disclosed herein allow for the voltage across the correspondingswitch capacitance in a boost converter system to discharge to zerovolts. In such examples disclosed herein, full soft switching (e.g.,zero voltage switching) of the switching device is enabled during alloperating conditions of a boost converter system. Moreover, examplesdisclosed herein enable an increase in the switching frequency (e.g.,increase to 1-megahertz for a power converter utilizing a super-junction(S-J) silicon transistor) of the boost converter system as a result ofthe reduced switching losses. As such, in examples disclosed herein, theincrease in switching frequency enables an increase in power density.Examples disclosed herein enable zero voltage switching under alloperating conditions in a boost converter, or any suitable powerconverter (e.g., buck converter, buck-boost converter, etc.).

In examples disclosed herein, a power converter utilizing S-J silicontransistors is operable utilizing a switching frequency around1-megahertz. Additionally, a power converter utilizing gallium nitrideswitching device is operable utilizing a switching frequency in the2-megahertz to 3-megahertz range. In such examples disclosed herein, theincrease in switching frequency (e.g., 1-megahertz, 2-megahertz to3-megahertz, etc.) is high enough above 150 kilohertz to have asignificant effect on the size and cost the power converter system(e.g., component sizes of a corresponding electromagnetic interferencefilter (EMI) is reduced as compared to power converter systems notutilizing exampled disclosed herein).

FIG. 3 is a schematic illustration of an example boost converter system300 including an example compensation network 302 to reduce switchingloss in the boost converter system 300. The boost converter system 300includes the compensation network 302, an example inductor 304, anexample capacitor 306, an example switching device 308, an example diode310, an example load 312, an example switch capacitance 314, an examplevoltage source 316, and an example controller 318. Moreover, thecompensation network 302 includes an example comparator 320, an examplelogic gate 322, an example ZVS switch 324, an example first resistor326, and an example second resistor 328.

Illustrated in the example of FIG. 3, the compensation network 302 iscoupled to an example input voltage node 303 (e.g., input node), anexample switch voltage node 305, and an example output voltage node 307(e.g., output node). In FIG. 3, the compensation network 302 is coupledto the input voltage node 303 to obtain an example input voltage signal(line 327). Additionally, the compensation network 302 is coupled to theoutput voltage node 307 to obtain an example output voltage signal (line311). The compensation network 302 may be implemented using hardwarelogic, machine readable instructions, hardware implemented statemachines, etc., and/or a combination thereof. The operation of thecompensation network 302 is explained in further detail below, inconnection with the components included in the compensation network 302.

In FIG. 3, the inductor 304 is coupled to the input voltage node 303 andto the switch voltage node 305. The capacitor 306 is coupled to theoutput voltage node 307 and to an example reference rail 336. The boostconverter system 300 may include components (e.g., capacitors,inductors, inductive elements, capacitive elements, etc.) that, whendriven by the controller 318 convert the voltage at the input voltagenode 303 to a desired output voltage at the output voltage node 307.

In the example of FIG. 3, the switching device 308 is an n-channelmetal-oxide-semiconductor field-effect transistor (NMOS). The switchingdevice 308 includes an example gate terminal 330, and example drainterminal 332, and an example source terminal 334. In FIG. 3, gateterminal 330 of the switching device 308 is coupled to the controller318, the drain terminal 332 of switching device 308 is coupled to theswitch voltage node 305, and the source terminal 334 of the switchingdevice 308 is coupled to the reference rail 336. In other examplesdisclosed herein, the switching device 308 may be any suitable switchingdevice (e.g., p-channel metal-oxide-semiconductor field-effecttransistor (PMOS), a high electron mobility transistor (HEMT), bi-polarjunction transistor (BJT), a diode, a transistor produced using siliconsubstrate, a gallium nitride transistor and/or switching device, etc.).

In the example of FIG. 3, the diode 310 includes an example anodeterminal 338, and example cathode terminal 340. In FIG. 3, the anodeterminal 338 of the diode 310 is coupled to the switch voltage node 305and the cathode terminal 340 of the diode 310 is coupled to the outputvoltage node 307. In other examples disclosed herein, the diode 310 maybe any suitable device (e.g., PMOS, NMOS, a high electron mobilitytransistor (HEMT), bi-polar junction transistor (BJT), a transistorproduced using silicon substrate, a gallium nitride transistor and/orswitching device, etc.) utilized as a rectifying device for the boostconverter system 300.

In FIG. 3, the load 312 is a resistive load coupled to the outputvoltage node 307 and the example reference rail 336. In the example ofFIG. 3, the load 312 is coupled to the output voltage node 307 to obtainand/or otherwise consume the voltage and/or current provided via theboost converter system 300. In other examples disclosed herein, the load312 may be any other suitable load (e.g., capacitive load, inductiveload, capacitive-inductive load, etc.,) utilized in any suitableelectrical system. For example, the load 312 may be traction inverter inan electric vehicle (EV), a hybrid electric vehicle (HEV), or a load inany suitable power electronic application.

In the example illustration of FIG. 3, the switch capacitance 314represents the inherent drain-to-source capacitance of the switchingdevice 308 and/or any stray capacitance of devices coupled to theswitching device 308. When the switching device 308 is disabled (e.g.,not conducting) and the diode 310 conducts, the voltage across theswitch capacitance 314 is equivalent to the voltage across the capacitor306 (e.g., the output voltage) plus the voltage drop from the anodeterminal 338 to the cathode terminal 340 of the diode 310.

In FIG. 3, the voltage source 316 provides a direct current (DC) voltageto the boost converter system 300. In other examples disclosed herein,the voltage source 316 may provide a rectified alternating current (AC)voltage to the boost converter system 300. The voltage source 316 may beimplemented using any suitable voltage source (e.g., battery, output ofa transformer, etc.).

In the example of FIG. 3, the controller 318 controls the enable signal(line 313) for the switching device 308. As described above, thecontroller 318 enables and disables the switching device 308 to controlcurrent conducting though the boost converter system 300. In examplesdisclosed herein, the controller 318 operates as a full ZVS controller.For example, the controller 318 generates and/or otherwise provides theenable signal (line 313) to the switching device 308 in response tomonitoring that the voltage across the switching device 308 is zerovolts (e.g., zero voltage switching). The controller 318 may senseand/or otherwise measure the voltage across the switching device 308using any suitable voltage sensing device and/or method.

In addition, the controller 318 is coupled to the compensation network302 to provide an example peak threshold signal (line 329). Thecontroller 318 provides the peak threshold signal (line 329) for alength of time determined based on, at least, the input voltage, theoutput voltage, and the inductance of the inductor 304. In examplesdisclosed herein, the controller 318 generates the peak threshold signal(line 329) when the voltage at the switch voltage node 305 rings to apeak (e.g., rising edge). The controller 318 may be implemented usinghardware logic, machine readable instructions, hardware implementedstate machines, etc., and/or a combination thereof.

In the example illustrated in FIG. 3, the comparator 320 includes anexample first input terminal 342, an example second input terminal 344,and an output terminal 346. In FIG. 3, the first input terminal 342 iscoupled to the input voltage node 303 and the second input terminal 344is coupled to an example divided output voltage node 315. The comparator320 compares the voltage at the input voltage node 303 with the voltageat the divided output voltage node 315. In the example of FIG. 3, thefirst resistor 326 and the second resistor 328 are equivalent, orsubstantially similar, resistors. In the topology illustrated in FIG. 3,the first resistor 326 and the second resistor 328 act as a voltagedivider, ensuring half of the output voltage signal (line 311) is at thedivided output voltage node 315. Therefore, the comparator 320effectively compares the input voltage signal (line 327) with half ofthe output voltage signal (line 311). In operation, the comparator 320generates an example indication signal (line 317) in response todetermining the voltage of the input voltage signal (line 327) isgreater than the voltage at the divided output voltage node 315.Therefore, the operation of the compensation network 302 may be enabledwhen the comparator 320 determines the voltage of the input voltagesignal (line 327) is greater than half of the voltage of the outputvoltage signal (line 311).

In FIG. 3, the logic gate 322 includes a first example input terminal348, a second example input terminal 350, and an example output terminal352. In FIG. 3, the first input terminal 348 of the logic gate 322 iscoupled to the output terminal 346 of the comparator 320, the secondinput terminal 350 of the logic gate 322 is coupled to the controller318, and the output terminal 352 of the logic gate 322 is coupled to anexample gate terminal 354 of the ZVS switch 324. In the topologyillustrated in FIG. 3, the logic gate 322 is a logic-AND gate.Additionally or alternatively, the logic gate 322 may be any suitablelogic gate utilized to obtain the indication signal (line 317) andgenerate an example trigger signal (line 319). In operation, the logicgate 322 provides trigger signal (line 319) in response to determiningthe indication signal (line 317) is a logic-high signal and the peakthreshold signal (line 329) is a logic-high signal. In examplesdisclosed herein, the peak threshold signal (line 329) is generated bythe controller 318, in response to the controller 318 monitoring thevoltage at the switch voltage node 305 is at a peak (e.g., the ringingpeak of the switch capacitance 314).

In the example illustrated in FIG. 3, the ZVS switch 324 includes thegate terminal 354, and example drain terminal 356, and an example sourceterminal 358. In examples disclosed herein, the drain terminal 356and/or the source terminal 358 may be referred to as current terminals.In the topology of FIG. 3, the gate terminal 354 is coupled to theoutput terminal 352 of the logic gate 322, the drain terminal 356 iscoupled to the output voltage node 307, and the source terminal 358 iscoupled to the switch voltage node 305. The ZVS switch 324 is an NMOSdevice that is physically smaller than the switching device 308. Forexample, the ZVS switch 324 is configured to conduct a small amount ofcurrent (e.g., 1 milliampere, etc.) as compared to the switching device308 that conducts a large amount of current (e.g., 1 ampere, 5 amperes,etc.). The ZVS switch 324 is coupled in parallel with the diode 310 toconduct a negative current (e.g., negative 1 milliampere) with respectto the polarity of the current conducting through the inductor 304. Inoperation, when the ZVS switch 324 is enabled, a small current (e.g., 1milliampere) will conduct from the drain terminal 356 to the sourceterminal 358. As such, the current conducting though the ZVS switch 324conducts through the inductor 304 and allows for the discharge ofvoltage across the switch capacitance 314.

In addition, by generating the peak threshold signal (line 329) when thevoltage at the switch voltage node 305 (e.g., the voltage at the sourceterminal 358) is at a peak (e.g., the ringing peak of the switchcapacitance 314), the topology of FIG. 3 ensures the ZVS switch 324 maybe enabled when there is a minimal voltage drop (e.g., 0 volts) from thedrain terminal 356 to the source terminal 358. For example, the peakthreshold signal (line 329) is generated when the voltage at the switchvoltage node 305 (e.g., the voltage at the source terminal 358) is at apeak (e.g., the ringing peak of the switch capacitance 314). Because thevoltage across the switch capacitance 314 may ring to a peak voltagesubstantially similar to the output voltage (e.g., the voltage at theoutput voltage node 307 plus the voltage drop across the diode 310), theZVS switch 324 is enabled when there is a minimal voltage drop (e.g., 0volts, 0.1 volts, etc.) from the drain terminal 356 to the sourceterminal 358.

In the example of FIG. 3, the controller 318 generates the peakthreshold signal (line 329) for a threshold duration. In such examplesdisclosed herein, the threshold duration may be calculated by thecontroller 318. The threshold duration may correspond to the length oftime in which to enable the ZVS switch 324. Additionally oralternatively, any suitable method of determining the threshold duration(e.g., conduction time and/or current conduction amount) with respect tothe ZVS switch 324 may be used.

In an example operation of the boost converter system 300, when theswitching device 308 is enabled (e.g., turned on or conducting), theinput voltage is applied across the inductor 304, thereby causing theinductor current to increase. After the current through the inductor 304increases to a desired value, the switching device 308 is disabled(e.g., turned off or not conducting). As a result, the inductor currentdischarges through the diode 310 and into the load 312. The currentthrough the inductor 304 discharges until reaching zero amperes.

Further in such example operation, after the current in the inductor 304discharges to zero amperes and the diode 310 no longer conducts, theswitch capacitance 314 will resonate with the inductor 304 and thevoltage across the switch capacitance 314 will ring down. If the inputvoltage of the input voltage source 316 is lower than half the outputvoltage (e.g., the voltage at the output voltage node 307), then thevoltage at the switch voltage node 305 rings down to zero volts, or evenbelow zero volts, thereby enabling the turn on of the switching device308 with zero volts across it. In such a scenario, switching losses ofthe switching device 308 are eliminated or substantially reduced.

If the input voltage of the input voltage source 316 is greater thanhalf the output voltage (e.g., the voltage at the output voltage node307), then the voltage at the switch voltage node 305 (e.g., the voltageat the source terminal 358 of the ZVS switch 324) will not ring to avalley peak of zero volts. In such a scenario, the ZVS switch 324 isturned on to allow current to flow through the inductor 304 and into theinput voltage source 316. Since the ZVS switch 324 is on, the inductorcurrent will go to zero amperes and will build up in the negativedirection. The negative current builds up in the inductor 304 longenough to create sufficient negative current in the inductor 304 tocompletely, or substantially, discharge the voltage at the switchvoltage node 305 (e.g., the voltage at the source terminal 358 of theZVS switch 324) when the ZVS switch 324 is turned off. The ZVS switch324 is enabled if the voltage of the input voltage source is greaterthan half voltage at the output voltage node 307.

Furthermore, switching losses of the ZVS switch 324 can be minimized byenabling (e.g., turning on) the ZVS switch 324 with a minimaldrain-to-source voltage (V_(DS)). This can be achieved by turning it onat the peak of the resonant ring. For example, an optimal time to enablethe ZVS switch 324 is when the voltage at the source terminal 358 of theZVS switch 324 rings to a peak. Because the ringing peak of the voltageat the source terminal 358 is equivalent to the output voltage plus thevoltage drop across the diode 310, the ZVS switch 324 is enabled withzero, or minimal, drain-to-source voltage VDS.

FIG. 4 is a plot 400 of various voltage, current, and enable signalsversus time in the boost converter system 300 of FIG. 3. FIG. 4illustrates an example switch node voltage signal (line 402), an exampleinductor current signal (line 404), an example enable transistor triggersignal (line 406), and an example switching device enable signal (line408), and an example enable switch current (line 410). The voltage,current, and enable signals of FIG. 4 represent respective similarvoltage, current, and enable signals occurring during operation of FIG.3. For example, the switch node voltage signal (line 402) may representthe switch node voltage signal of the switch voltage node 305 of FIG. 3,the inductor current signal (line 404) may represent the currentconducting through the inductor 304 of FIG. 3, the enable transistortrigger signal (line 406) may represent the trigger signal (line 319) ofFIG. 3, the switching device enable signal (line 408) may represent theenable signal (line 313) of FIG. 3, and the enable switch current (line410) may represent the current conducting through the ZVS switch 324 ofFIG. 3. Additionally, the operating conditions portrayed in FIG. 4represent when the magnitude of the input voltage signal (e.g., theinput voltage signal from the voltage source 316) is 365 volts and themagnitude of the output voltage signal (e.g., the output voltage signal(line 311)) is 390 volts.

Illustrated in FIG. 4, at a first example time interval 401, theinductor current signal (line 404) reaches zero amperes. As such, theswitch node voltage signal (line 402) rings to a trough that does notreach zero volts. At a second example time interval 403, the enabletransistor trigger signal (line 406) becomes a logic high, therebycausing the conduction of a small current (e.g., 0.37 amperes) throughthe inductor (line 404) and into the input voltage. As a result, theswitch node voltage signal (line 402) decreases to zero volts. At athird example time interval 405, the switch node voltage signal (line402) decreases to zero volts and, therefore, the switching device enablesignal (line 408) becomes a logic high. Indicated by the plot 400 inFIG. 4, full ZVS control (e.g., enabling the switching device when theswitch node voltage signal (line 402) is zero volts) is achievable.

FIG. 5 is a plot 500 of the current conducting through the switchingdevice 308 of FIG. 3 versus time during quasi-resonant operation. InFIG. 5, an example first quasi-resonant (QR) switching device currentsignal (line 502) represents the current conducting through theswitching device 308 of the boost converter system 300 if thecompensation network 302 is not utilized. Illustrated in FIG. 5, thefirst QR switching device current signal (line 502) reaches a magnitudeof 150 amperes. On the other hand, an example second QR switching devicecurrent signal (line 504) represents the current conducting through theswitching device 308 of the boost converter system 300 if thecompensation network 302 is utilized. As such, the second QR switchingdevice current signal (line 504) reaches a magnitude of about 1.5amperes. As illustrated in FIG. 5, the switching losses experienced inthe boost converter system 300 if the compensation network 302 isutilized during quasi-resonant switching operation is reduced (e.g., thesecond QR switching device current signal (line 504) reaches 1.5 amperesand the first QR switching device current signal (line 502) reaches 150amperes).

FIGS. 6A-6B are plots 610, 620 of various voltage and current signals ofthe switching device 308 of FIG. 3, shown on a more focused timescalethan plot 500 in FIG. 5. More specifically, the illustration of FIGS.6A-6B include a more refined time scale on the x-axis as in FIG. 5. InFIG. 6A, an example first quasi-resonant (QR) switching device currentsignal (line 602) represents the current conducting through theswitching device 308 of the boost converter system 300 if thecompensation network 302 is not utilized. Additionally, an examplevoltage signal (line 604) represents the voltage across the switchingdevice 308 (e.g., the voltage across the switch capacitance 314) if thecompensation network 302 is not utilized. Between an example first timeinterval 601 and an example second time interval 603, the voltage signal(line 604) decreases to a non-zero voltage (e.g., 250 volts). At thesecond time interval 603, the controller 318 generates the enable signal(line 313) for the switching device 308 and, for a brief period of time(e.g., 1 microsecond), there is a 250-volt potential across theswitching device 308. As such, at the second time interval 603, the QRswitching device current signal (line 602) illustrates a discharge(e.g., spikes to and/or conducts) of 15 amperes of current (e.g., adischarge of 15 amperes of current from the switch capacitance 314).

In FIG. 6B, an example second quasi-resonant (QR) switching devicecurrent signal (line 606) represents the current conducting through theswitching device 308 of the boost converter system 300 if thecompensation network 302 is utilized. At an example third time interval605, the QR second switching device current signal (line 606) is lessthan zero amperes and, therefore, the voltage across the correspondingswitching device 308 reaches a lower voltage than if the compensationnetwork 302 is not utilized. As such, at a fourth time interval 607, thesecond QR switching device current signal (line 606) illustrates adischarge (e.g., spikes to and/or conducts) of 1.6 amperes of current(e.g., a discharge of 1.6 amperes of current from the switch capacitance314).

FIG. 7 is a plot 700 of the current conducting through the switchingdevice 308 of FIG. 3 versus time for zero voltage switching operation.In FIG. 7, an example first ZVS switching device current signal (line702) represents the current conducting through the switching device 308of the boost converter system 300 if the compensation network 302 is notutilized. Illustrated in FIG. 7, the first ZVS switching device currentsignal (line 702) reaches a magnitude of 6 amperes. On the other hand,an example second ZVS switching device current signal (line 704)represents the current conducting through the switching device 308 ofthe boost converter system 300 if the compensation network 302 isutilized. As such, the second ZVS switching device current signal (line704) reaches a magnitude of about 2 amperes. As illustrated in FIG. 7,the switching losses experienced in the boost converter system 300 ifthe compensation network 302 is utilized during ZVS operation islikewise reduced (e.g., the second ZVS switching device current signal(line 704) reaches 2 amperes and the first ZVS switching device currentsignal (line 702) reaches 6 amperes).

FIGS. 8A-8B are plots 810, 820 of various voltage and current signals ofthe switching device 308 of FIG. 3, shown on a more focused timescalethan the plot 700 in FIG. 7. More specifically, the illustration ofFIGS. 8A-8B include a more refined time scale on the x-axis as in FIG.7. In FIG. 8A, an example first ZVS switching device current signal(line 802) represents the current conducting through the switchingdevice 308 of the boost converter system 300 if the compensation network302 is not utilized. Additionally, an example voltage signal (line 804)represents the voltage across the switching device 308 (e.g., thevoltage across the switch capacitance 314) if the compensation network302 is not utilized. Between an example first time interval 801 and anexample second time interval 803, the voltage signal (line 804)decreases to a non-zero voltage (e.g., 10 volts). At the second timeinterval 803, the controller 318 generates the enable signal (line 313)for the switching device 308 and, for a brief period of time (e.g., 1microsecond), there is a 10-volt potential across the switching device308. As such, at the second time interval 803, the ZVS switching devicecurrent signal (line 802) illustrates a discharge of 5 amperes ofcurrent (e.g., a discharge of 5 amperes of current from the switchcapacitance 314).

In FIG. 8B, an example second ZVS switching device current signal (line806) represents the current conducting through the switching device 308of the boost converter system 300 if the compensation network 302 isutilized. At an example third time interval 805, the second ZVSswitching device current signal (line 806) is less than zero amperesand, therefore, the voltage across the corresponding switching device308 reaches a lower voltage than if the compensation network 302 is notutilized. As such, at a fourth time interval 807, the second ZVSswitching device current signal (line 806) illustrates a discharge(e.g., spikes to and/or conducts) of 2 amperes of current (e.g., adischarge of 2 amperes of current from the switch capacitance 314).

FIG. 9 is a plot 900 of current conducting through the inductor (line902) of FIG. 3 versus time and a frequency domain representation 904 ofthe current conducting through the inductor 304 of FIG. 3. In FIG. 9,between an example first time period 901 and an example second timeperiod 903, the current conducting through the inductor 304 is zeroamperes. As such, the frequency domain representation 904 indicates theharmonic content of the current conducting through the inductor 304(line 902) when the power supplied by the boost converter system 300decreases (e.g., decreases below 65 watts). A table illustrating theharmonic content and the International Electrotechnical Commission (IEC)standard versus harmonic order is shown below, in Table 1.

TABLE 1 Harmonic Harmonic Content IEC Standard Order (mA/W) (mA/W) 30.630227743 3.5 5 0.382608696 1.9 7 0.200828157 1 9 0.13747412 0.5 110.075196687 0.35 13 0.033457557 0.296

FIG. 10 is a schematic illustration of an example buck converter system1000 including an example compensation network 1001 to reduce switchingloss in the buck converter system 1000. The buck converter system 1000includes an example input voltage source 1002, an example switchingdevice 1004, an example diode 1006, an example switch capacitance 1008,an example inductor 1010, and an example capacitor 1012. The buckconverter system 1000 also includes an example load 1058. Moreover, thecompensation network 1001 includes an example reference determiner 1014,an example comparator 1016, an example logic gate 1018, and an exampleZVS switch 1020.

Illustrated in the example of FIG. 10, the compensation network 1001 iscoupled to an example input voltage node 1003 (e.g., input node), anexample switch voltage node 1005, and an example output voltage node1007 (e.g., output node). In FIG. 10, the compensation network 1001 iscoupled to the input voltage node 1003 to obtain an example inputvoltage signal (line 1015). Additionally, the compensation network 1001is coupled to the output voltage node 1007 to obtain an example outputvoltage signal (line 1011). The compensation network 1001 may beimplemented using hardware logic, machine readable instructions,hardware implemented state machines, etc., and/or a combination thereof.The operation of the compensation network 1001 is explained in furtherdetail below, in connection with the components included in thecompensation network 1001.

In FIG. 10, the input voltage source 1002 provides a direct current (DC)voltage to the buck converter system 1000. In other examples disclosedherein, the input voltage source 1002 may provide a rectified AC voltageto the buck converter system 1000. The input voltage source 1002 may beimplemented using any suitable voltage source (e.g., battery, output ofa transformer, etc.).

In the example of FIG. 10, the switching device 1004 is an n-channelmetal-oxide-semiconductor field-effect transistor (NMOS). The switchingdevice 1004 includes an example gate terminal 1022, and example drainterminal 1024, and an example source terminal 1026. In FIG. 10, the gateterminal 1022 of the switching device 1004 is coupled to an examplecontroller 1028, the drain terminal 1024 of the switching device 1004 iscoupled to the input voltage node 1003, and the source terminal 1026 ofthe switching device 1004 is coupled to the switch voltage node 1005. Inother examples disclosed herein, the switching device 1004 may be anysuitable switching device (e.g., p-channel metal-oxide-semiconductorfield-effect transistor (PMOS), a high electron mobility transistor(HEMT), bi-polar junction transistor (BJT), a diode, a transistorproduced using silicon substrate, a gallium nitride transistor and/orswitching device, etc.).

In the example of FIG. 10, the diode 1006 includes an example anodeterminal 1030 and example cathode terminal 1032. In FIG. 10, the cathodeterminal 1032 of the diode 1006 is coupled to the switch voltage node1005 and the anode terminal 1030 of the diode 1006 is coupled to anexample reference rail 1034. In other examples disclosed herein, thediode 1006 may be any suitable switching device (e.g., PMOS, NMOS, ahigh electron mobility transistor (HEMT), bi-polar junction transistor(BJT), a transistor produced using silicon substrate, a gallium nitridetransistor and/or switching device, etc.) utilized as a rectifyingdevice for the buck converter system 1000.

In the example illustration of FIG. 10, the switch capacitance 1008represents the inherent drain-to-source capacitance of the switchingdevice 1004 and/or any stray capacitance of devices coupled to theswitching device 1004.

In FIG. 10, the inductor 1010 is coupled to the switch voltage node 1005and to the output voltage node 1007. The capacitor 1012 is coupled tothe output voltage node 1007 and to an example reference rail 1034. Thebuck converter system 1000 may include components (e.g., capacitors,inductors, inductive elements, capacitive elements, etc.) that, whendriven by the controller 1028 convert the voltage at the input voltagenode 1003 to a desired output voltage at the output voltage node 1007.

In the example of FIG. 10, the reference determiner 1014 includes aninput terminal 1036 and an output terminal 1038. In FIG. 10, the inputterminal 1036 of the reference determiner 1014 is coupled to the inputvoltage node 1003 and the output terminal 1038 of the referencedeterminer 1014 is coupled to the comparator 1016. The referencedeterminer 1014 provides a reference signal to the comparator 1016 inwhich the reference signal is equivalent to, or substantially similarto, half the input voltage signal (line 1015). The reference determiner1014 may be implemented using any suitable analog, digital, hardware,software, and/or firmware apparatus to generate a signal equivalent tohalf of the input voltage signal (line 1015).

In the example illustrated in FIG. 10, the comparator 1016 includes anexample first input terminal 1040, an example second input terminal1042, and an example output terminal 1044. In FIG. 10, the first inputterminal 1040 of the comparator 1016 is coupled to the output voltagenode 1007 and the second input terminal 1042 of the comparator 1016 iscoupled to the output terminal 1038 of the reference determiner 1014.The comparator 1016 compares the voltage at the output voltage node 1007with the half the voltage of the input voltage signal (line 1015).Therefore, the comparator 1016 effectively compares half the of theinput voltage signal (line 1015) with the output voltage signal (line1011). In operation, the comparator 1016 generates an example indicationsignal (line 1017) in response to determining half the input voltagesignal (line 1015) is less than the voltage at the output voltage node1007. Therefore, the operation of the compensation network 1001 may beenabled when the comparator 1016 determines half the magnitude of theinput voltage signal (line 1015) is less than the magnitude of theoutput voltage signal (line 1011).

In FIG. 10, the logic gate 1018 includes an example first input terminal1046, an example second input terminal 1048, and an example outputterminal 1050. In FIG. 10, the first input terminal 1046 of the logicgate 1018 is coupled to the output terminal 1044 of the comparator 1016,the second input terminal 1048 of the logic gate 1018 is coupled to thecontroller 1028, and the output terminal 1050 of the logic gate 1018 iscoupled to the to the ZVS switch 1020. In the topology illustrated inFIG. 10, the logic gate 1018 is a logic-AND gate. Additionally oralternatively, the logic gate 1018 may be any suitable logic gateutilized to obtain the indication signal (line 1017) and generate anexample trigger signal (line 1019). In operation, the logic gate 1018provides trigger signal (line 1019) in response to determining theindication signal (line 1017) is a logic-high signal and an example peakthreshold signal (line 1027) is a logic-high signal. In examplesdisclosed herein, the peak threshold signal (line 1027) is generated bythe controller 1028, in response to the controller 1028 monitoring themagnitude of the voltage at the switch voltage node 1005 is at a trough(e.g., the ringing trough of the switch capacitance 1008).

In the example illustrated in FIG. 10, the ZVS switch 1020 includes anexample gate terminal 1052, and example drain terminal 1054, and anexample source terminal 1056. In examples disclosed herein, the drainterminal 1054 and/or the source terminal 1056 may be referred to asrespective current terminals. In the topology of FIG. 10, the gateterminal 1052 is coupled to output terminal 1050 the logic gate 1018,the drain terminal 1054 is coupled to the switch voltage node 1005, andthe source terminal 1056 is coupled to the reference rail 1034. The ZVSswitch 1020 is an NMOS device that is physically smaller than theswitching device 1004. For example, when conducting, the ZVS switch 1020conducts a small amount of current (e.g., 1 milliampere, etc.) comparedto the first switching device 1004 that conducts a large amount ofcurrent (e.g., 1 ampere, 5 amperes, etc.). The ZVS switch 1020 iscoupled in parallel with the diode 1006 to conduct a negative current(e.g., negative 1 milliamperes) with respect to the polarity of thecurrent conducting through the inductor 1010. In operation, when theswitching device 1004 is enabled a negative current (e.g., 1milliampere) will conduct from the drain terminal 1054 to the sourceterminal 1056.

In addition, by generating the peak threshold signal (line 1027) whenthe voltage at the switch voltage node 1005 (e.g., the voltage at thedrain terminal 1054) is at a trough (e.g., the ringing trough of theswitch capacitance 1008), the topology of FIG. 10 ensures the ZVS switch1020 may be enabled when there is a minimal voltage drop (e.g., 0 volts)from the drain terminal 1054 to the source terminal 1056.

In the example of FIG. 10, the controller 1028 generates the peakthreshold signal (line 1027) for a threshold duration. In such examplesdisclosed herein, the threshold duration may be calculated by thecontroller 1028. The threshold duration may correspond to the length oftime in which to enable the ZVS switch 1020. Additionally oralternatively, any suitable method of determining the threshold duration(e.g., conduction time and/or current conduction amount) with respect tothe ZVS switch 1020 may be used.

In the example of FIG. 10, the controller 1028 controls the enablesignal (line 1013) for the switching device 1004. As described above,the controller 1028 enables and disables the switching device 1004 tocontrol current conducting though the buck converter system 1000. Inexamples disclosed herein, the controller 1028 operates as a full ZVScontroller.

In addition, the controller 1028 is coupled to the compensation network1001 to provide the example peak threshold signal (line 1027). Thecontroller provides the peak threshold signal (line 1027) for a lengthof time determined based on, at least, the input voltage, the outputvoltage, the inductance of the inductor 1010. In examples disclosedherein, the controller 1028 generates the peak threshold signal (line1027) when the magnitude of the voltage at the switch voltage node 1005is at a trough (e.g., falling edge). The controller 1028 may beimplemented using hardware logic, machine readable instructions,hardware implemented state machines, etc., and/or a combination thereof.

In FIG. 10, the load 1058 is a resistive load coupled to the outputvoltage node 1007 and the example reference rail 1034. In the example ofFIG. 10, the load 1058 is coupled to the output voltage node 1007 toobtain and/or otherwise consume the voltage and/or current provided viathe buck converter system 1000. In other examples disclosed herein, theload 1058 may be any other suitable load (e.g., capacitive load,inductive load, capacitive-inductive load, etc.,) utilized in anysuitable electrical system. For example, the load 1058 may be tractioninverter in an electric vehicle (EV), a hybrid electric vehicle (HEV),or a load in any suitable power electronic application.

In an example operation of the buck converter system 1000, when theswitching device 1004 is enabled (e.g., turned on or conducting), theinput voltage is applied to the inductor 1010 and to the output node1007, thereby causing the inductor current to increase. After thecurrent in the inductor 1010 increases to a desired value, the switchingdevice 1004 is disabled (e.g., turned off or not conducting). As aresult, the inductor current discharges into the load 1058. The currentthrough the inductor 1010 discharges until reaching zero amperes.

After the current in the inductor 1010 discharges to zero amperes andthe diode 1006 no longer conducts, the switch capacitance 1008 willresonate with the inductor 1010 and the voltage across the switchcapacitance 1008 will ring from the input voltage (e.g., the inputvoltage) to zero. If the output voltage (e.g., the voltage at the outputvoltage node 1007) is less than half of the voltage of the input voltagesource 1002, then the voltage at the switch voltage node 1005 rings tovoltage equal to the input voltage source 1002, thereby allowing theturn on of the switching device 1004 with zero volts across it. In sucha scenario, switching losses of the switching device 1004 are eliminatedor substantially reduced.

If the output voltage (e.g., the voltage at the output voltage node1007) is greater than half of the voltage of the input voltage source1002, then the voltage at the switch voltage node 1005 (e.g., thevoltage at the drain terminal 1054 of the ZVS switch 1020) will not ringto a voltage equal to the input voltage. In such a scenario, the ZVSswitch 1020 is turned on to allow current to flow from the outputvoltage node 1007, through the inductor 1010, and to the input voltagesource 1002. The ZVS switch 1020 may be allowed to conduct long enoughto create sufficient current in the inductor 1010 to completely, orsubstantially, discharge the voltage of the switch capacitance 1008 whenthe ZVS switch 1020 is turned off. The ZVS switch 1020 is enabled onlyif the output voltage (e.g., the voltage at the output voltage node1007) is greater than half of the voltage of the input voltage source.

Furthermore, switching losses of the ZVS switch 1020 can be minimized byenabling (e.g., turning on) the ZVS switch 1020 with a minimaldrain-to-source voltage (V_(DS)). This can be achieved by turning it onat the valley of the resonant ring (i.e., when the voltage across theZVS switch 1020 reaches a minimum value).

FIG. 11 is a schematic illustration of an example buck-boost convertersystem 1100 including an example compensation network 1101 to reduceswitching loss in the buck-boost converter system 1100. The buck-boostconverter system 1100 includes an example input voltage source 1102, anexample switching device 1104, an example diode 1106, an example switchcapacitance 1108, an example inductor 1110, and an example capacitor1112. The buck-boost converter system 1100 also includes an example load1152. Moreover, the compensation network 1101 includes an examplecomparator 1114, an example logic gate 1116, and an example enableswitch 1118.

Illustrated in the example of FIG. 11, the compensation network 1101 iscoupled to an example input voltage node 1103 (e.g., input node), anexample switch voltage node 1105, and an example output voltage node1107 (e.g., output node). In FIG. 11, the compensation network 1101 iscoupled to the input voltage node 1103 to obtain an example inputvoltage signal (line 1115). Additionally, the compensation network 1101is coupled to the output voltage node 1107 to obtain an example outputvoltage signal (line 1111). The compensation network 1101 may beimplemented using hardware logic, machine readable instructions,hardware implemented state machines, etc., and/or a combination thereof.The operation of the compensation network 1101 is explained in furtherdetail below, in connection with the components included in thecompensation network 1101.

In FIG. 11, the input voltage source 1102 provides a direct current (DC)voltage to the buck-boost converter system 1100. In other examplesdisclosed herein, the input voltage source 1102 may provide a rectifiedAC voltage to the buck-boost converter system 1100. The input voltagesource 1102 may be implemented using any suitable voltage source (e.g.,battery, output of a transformer, etc.).

In the example of FIG. 11, the switching device 1104 is an n-channelmetal-oxide-semiconductor field-effect transistor (NMOS). The switchingdevice 1104 includes an example gate terminal 1120, and example drainterminal 1122, and an example source terminal 1124. In FIG. 11, the gateterminal 1120 of the switching device 1104 is coupled to an examplecontroller 1126, the drain terminal 1122 of the switching device 1104 iscoupled to the input voltage node 1103, and the source terminal 1124 ofthe switching device 1104 is coupled to the switch voltage node 1105. Inother examples disclosed herein, the switching device 1104 may be anysuitable switching device (e.g., p-channel metal-oxide-semiconductorfield-effect transistor (PMOS), a high electron mobility transistor(HEMT), bi-polar junction transistor (BJT), a diode, a transistorproduced using silicon substrate, a gallium nitride transistor and/orswitching device, etc.).

In the example of FIG. 11, the diode 1106 includes an example anodeterminal 1128 and example cathode terminal 1130. In FIG. 11, the cathodeterminal 1130 terminal of the diode 1106 is coupled to the switchvoltage node 1105 and the anode terminal 1128 of the diode 1106 iscoupled to the output voltage node 1107. In other examples disclosedherein, the diode 1106 may be any suitable switching device (e.g., PMOS,NMOS, a high electron mobility transistor (HEMT), bi-polar junctiontransistor (BJT), a transistor produced using silicon substrate, agallium nitride transistor and/or switching device, etc.) utilized as arectifying device for the buck-boost converter system 1100.

In the example illustration of FIG. 11, the switch capacitance 1108represents the inherent drain-to-source capacitance of the switchingdevice 1104 and/or any stray capacitance of devices coupled to theswitching device 1104.

In FIG. 11, the inductor 1110 is coupled to the switch voltage node 1105and to an example reference rail 1132. The capacitor 1112 is coupled tothe output voltage node 1107 and to the reference rail 1132. Thebuck-boost converter system 1100 may include components (e.g.,capacitors, inductors, inductive elements, capacitive elements, etc.)that, when driven by the controller 1126 convert the voltage at theinput voltage node 1103 to a desired output voltage at the outputvoltage node 1107.

In the example illustrated in FIG. 11, the comparator 1114 includes anexample first input terminal 1134, an example second input terminal1136, and an example output terminal 1138. In FIG. 11, the first inputterminal 1134 of the comparator 1114 is coupled to the input voltagenode 1103 and the second input terminal 1136 of the comparator 1114 iscoupled to the output voltage node 1107. The comparator 1114 comparesthe voltage at the input voltage node 1103 with the voltage at theoutput voltage node 1107. The buck-boost converter system 1100 canincrease or decrease the voltage at the output voltage node 1107 withrespect to the voltage at the input voltage node 1103. In operation, thecomparator 1114 generates an example trigger signal (line 1119) inresponse to determining the input voltage signal (line 1115) is greaterthan the output voltage signal (line 1111). Therefore, the operation ofthe compensation network 1101 is enabled when the comparator 1114determines the input voltage signal (line 1115) is greater than theoutput voltage signal (line 1111).

In FIG. 11, the logic gate 1116 an example first input terminal 1140, anexample second input terminal 1142, and an example output terminal 1144.In FIG. 11, the first input terminal 1140 of the logic gate 1116 iscoupled to the output terminal 1138 of the comparator 1114, the secondinput terminal 1142 of the logic gate 1116 is coupled to the controller1126, and the output terminal 1144 of the logic gate 1116 is coupled toan example gate terminal 1146 of the enable switch 1118. In the topologyillustrated in FIG. 11, the logic gate 1116 is a logic-AND gate.Additionally or alternatively, the logic gate 1116 may be any suitablelogic gate utilized to obtain the indication signal (line 1117) andgenerate an example trigger signal (line 1119). In operation, the logicgate 1116 provides trigger signal (line 11119) in response todetermining the indication signal (line 1117) is a logic-high signal andan example peak threshold signal (line 1127) is a logic-high signal. Inexamples disclosed herein, the peak threshold signal (line 1127) isgenerated by the controller 1126, in response to the controller 1126monitoring the voltage at the switch voltage node 1105 is at a peak(e.g., the ringing peak of the switch capacitance 1108).

In the example illustrated in FIG. 11, the enable switch 1118 includesthe gate terminal 1146, and example drain terminal 1148, and an examplesource terminal 1150. In examples disclosed herein, the drain terminal1148 and/or the source terminal 1150 may be referred to as respectivecurrent terminals. In the topology of FIG. 11, the gate terminal 1146 iscoupled to the output terminal 1144 of the logic gate 1116, the drainterminal 1148 is coupled to the switch voltage node 1105, and the sourceterminal 1150 is coupled to the output voltage node 1107. The enableswitch 1118 is an NMOS device that is physically smaller than theswitching device 1104. For example, when conducting, the enable switch1118 conducts a small amount of current (e.g., 1 milliampere) comparedto the first switching device 1104 that conducts a large amount ofcurrent (e.g., 1 ampere, 5 amperes, etc.). The enable switch 1118 iscoupled in parallel with the diode 1106 to conduct a negative current(e.g., negative 1 milliamperes) with respect to the polarity of thecurrent conducting through the inductor 1110. In operation, when theenable switch 1118 is enabled, a small current (e.g., 1 milliampere,etc.) will conduct from the drain terminal 1123 to the source terminal1125.

In addition, by generating the peak threshold signal (line 1127) whenthe voltage at the switch voltage node 1105 (e.g., the voltage at thedrain terminal 1148) is at a peak (e.g., the ringing peak of the switchcapacitance 1108), the topology of FIG. 11 ensures the enable switch1118 may be enabled when there is a minimal voltage drop (e.g., 0 volts)from the drain terminal 1148 to the source terminal 1150.

If the buck-boost converter system 1100 is producing an output voltagesignal (line 1111) greater than the input voltage signal (line 1115),than the threshold duration of the negative current conducting throughthe enable switch 1118 may be determined in a manner similar to FIG. 3.Additionally or alternatively, if the buck-boost converter system 1100is producing an output voltage signal (line 1111) less than the inputvoltage signal (line 1115), then the threshold duration of the currentconducting through the enable switch 1118 may be determined in a mannersimilar to FIG. 10. Alternatively, any suitable method of determiningthe threshold duration may be used.

In the example of FIG. 11, the controller 1126 controls the enablesignal (line 1113) for the switching device 1104. As described above,the controller 1126 enables and disables the switching device 1104 tocontrol current conducting though the buck-boost converter system 1100.In examples disclosed herein, the controller 1126 operates as a full ZVScontroller. In FIG. 11, the controller 1126 may act in accordance as thecontroller illustrated in FIG. 3 and/or FIG. 10 (e.g., the controller318 and/or the controller 1028). The controller 1126 may be implementedusing hardware logic, machine readable instructions, hardwareimplemented state machines, etc., and/or a combination thereof.

In FIG. 11, the load 1152 is a resistive load coupled to the outputvoltage node 1107 and an example reference rail 1132. In the example ofFIG. 11, the load 1152 is coupled to the output voltage node 1107 toobtain and/or otherwise consume the voltage and/or current provided viathe buck-boost converter system 1100. In other examples disclosedherein, the load 1152 may be any other suitable load (e.g., capacitiveload, inductive load, capacitive-inductive load, etc.,) utilized in anysuitable electrical system. For example, the load 1152 may be tractioninverter in an electric vehicle (EV), a hybrid electric vehicle (HEV),or a load in any suitable power electronic application.

In addition, the controller 1126 is coupled to the compensation network1101 to provide the example peak threshold signal (line 1127). Thecontroller 1126 provides the peak threshold signal (line 1127) for alength of time determined based on at least the input voltage, theoutput voltage, the inductance of the inductor 1110. In examplesdisclosed herein, the controller 1126 generates the peak thresholdsignal (line 1127) when the voltage at the switch voltage node 1105 isat a peak (e.g., rising edge). The controller 1126 may be implementedusing hardware logic, machine readable instructions, hardwareimplemented state machines, etc., and/or a combination thereof.

In an example operation of the buck-boost converter system 1100, whenthe switching device 1104 is enabled (e.g., turned on or conducting),thereby causing the inductor current to increase. After the current inthe inductor 1110 increases to a desired value, the switching device1104 is disabled (e.g., turned off or not conducting). As a result, theinductor current discharges into the load 1152. The current through theinductor 1110 discharges until reaching zero amperes.

After the current in the inductor 1110 discharges to zero amperes andthe diode 1106 no longer conducts, the switch capacitance 1108 willresonate with the inductor 1110 and the voltage across the switchcapacitance 1108 will ring from a voltage equal to the input voltage(e.g., the voltage of the input voltage source 1102) plus the outputvoltage (e.g., the voltage at the output voltage node 1107) towards zerovolts. If the output voltage (e.g., the voltage at the output voltagenode 1107) is greater than the voltage of the input voltage source 316,then the voltage across the switch capacitance 1108 will ring to zero,thereby allowing the turn on of the switching device 1104 with zerovolts across it. In such a scenario, switching losses of the switchingdevice 1104 are eliminated or substantially reduced.

If the output voltage (e.g., the voltage at the output voltage node1107) is less than the voltage of the input voltage source 1102, thenthe voltage across the switch capacitance 1108 will not ring to zerovolts. In such a scenario, the ZVS switch 1118 is turned on to allowcurrent to flow from the output voltage node 1107, through the ZVSswitch 1118, and through the inductor 1110. The ZVS switch 1118 may beallowed to conduct long enough to create sufficient current in theinductor 1110 to completely, or substantially, discharge the voltage ofthe switch capacitance 1108 when the ZVS switch 1118 is turned off. TheZVS switch 1118 is enabled if the voltage of the input voltage source1102 is greater than the output voltage (e.g., the voltage at the outputvoltage node 1107).

Furthermore, switching losses of the ZVS switch 1118 can be minimized byenabling (e.g., turning on) the ZVS switch 1118 with a minimaldrain-to-source voltage (V_(DS)). This can be achieved by turning it onat the peak of the resonant ring.

While an example manner of implementing the compensation network 302 ofFIG. 3, the compensation network 1001 of FIG. 10, and/or thecompensation network 1101 of FIG. 11 is illustrated in FIGS. 3, 10,and/or 11, one or more of the elements, processes and/or devicesillustrated in FIGS. 3, 10, and/or 11 may be combined, divided,re-arranged, omitted, eliminated and/or implemented in any other way.Further, the example comparator 320, the example logic gate 322, theexample ZVS switch 324, the example first resistor 326, the examplesecond resistor 328 and/or, more generally, the example compensationnetwork 302 of FIG. 3, the example reference determiner 1014, theexample comparator 1016, the example logic gate 1018, the example ZVSswitch 1020, and/or, more generally, the example compensation network1002 of FIG. 10, the example comparator 1114, the example logic gate1116, the example enable switch 1118, and/or, more generally, theexample compensation network 1102 of FIG. 11, may be implemented byhardware, software, firmware and/or any combination of hardware,software and/or firmware. Thus, for example, any the example comparator320, the example logic gate 322, the example ZVS switch 324, the examplefirst resistor 326, the example second resistor 328 and/or, moregenerally, the example compensation network 302 of FIG. 3, the examplereference determiner 1014, the example comparator 1016, the examplelogic gate 1018, the example ZVS switch 1020, and/or, more generally,the example compensation network 1002 of FIG. 10, the example comparator1114, the example logic gate 1116, the example enable switch 1118,and/or, more generally, the example compensation network 1102 of FIG. 11could be implemented by one or more analog or digital circuit(s), logiccircuits, programmable processor(s), programmable controller(s),graphics processing unit(s) (GPU(s)), digital signal processor(s)(DSP(s)), application specific integrated circuit(s) (ASIC(s)),programmable logic device(s) (PLD(s)) and/or field programmable logicdevice(s) (FPLD(s)). When reading any of the apparatus or system claimsof this patent to cover a purely software and/or firmwareimplementation, at least one of the example comparator 320, the examplelogic gate 322, the example ZVS switch 324, the example first resistor326, the example second resistor 328 and/or, more generally, the examplecompensation network 302 of FIG. 3, the example reference determiner1014, the example comparator 1016, the example logic gate 1018, theexample ZVS switch 1020, and/or, more generally, the examplecompensation network 1002 of FIG. 10, the example comparator 1114, theexample logic gate 1116, the example enable switch 1118, and/or, moregenerally, the example compensation network 1102 of FIG. 11 is/arehereby expressly defined to include a non-transitory computer readablestorage device or storage disk such as a memory, a digital versatiledisk (DVD), a compact disk (CD), a Blu-ray disk, etc. including thesoftware and/or firmware. Further still, the example compensationnetwork 302 of FIG. 3, the example compensation network 1001 of FIG. 10,and/or the example compensation network 1101 of FIG. 11 may include oneor more elements, processes and/or devices in addition to, or insteadof, those illustrated in FIGS. 3, 10, and/or 11, and/or may include morethan one of any or all of the illustrated elements, processes anddevices. As used herein, the phrase “in communication,” includingvariations thereof, encompasses direct communication and/or indirectcommunication through one or more intermediary components, and does notrequire direct physical (e.g., wired) communication and/or constantcommunication, but rather additionally includes selective communicationat periodic intervals, scheduled intervals, aperiodic intervals, and/orone-time events.

A flowchart representative of example hardware logic, machine readableinstructions, hardware implemented state machines, and/or anycombination thereof for implementing the compensation network 302 ofFIG. 3, the compensation network 1001 of FIG. 10, and/or thecompensation network 1101 of FIG. 11 is shown in FIG. 12. The machinereadable instructions may be one or more executable programs orportion(s) of an executable program for execution by one or morecomputer processors, one or more microcontrollers, etc. For example, themachine readable instructions may be executed by one or more integratedcircuits, logic circuits, microprocessors, GPUs, DSPs, or controllersfrom any desired family or manufacturer. For example, the one or moreintegrated circuits, logic circuits, microprocessors, GPUs, DSPs, orcontrollers may be semiconductor based (e.g., silicon based) device(s).The program may be embodied in software stored on a non-transitorycomputer readable storage medium such as non-volatile memory, volatilememory, etc., associated with the one or more computer processors, theone or more microcontrollers, etc., but the entire program and/or partsthereof could alternatively be executed by a device other than the oneor more computer processors, the one or more microcontrollers, etc.,and/or embodied in firmware or dedicated hardware. Further, although theexample program is described with reference to the flowchart illustratedin FIG. 12, many other methods of implementing the example compensationnetwork 302 of FIG. 3, the example compensation network 1001 of FIG. 10,and/or the example compensation network 1101 of FIG. 11 mayalternatively be used. For example, the order of execution of the blocksmay be changed, and/or some of the blocks described may be changed,eliminated, or combined. Additionally or alternatively, any or all ofthe blocks may be implemented by one or more hardware circuits (e.g.,discrete and/or integrated analog and/or digital circuitry, an FPGA, anASIC, a comparator, an operational-amplifier (op-amp), a logic circuit,etc.) structured to perform the corresponding operation withoutexecuting software or firmware.

The machine readable instructions described herein may be stored in oneor more of a compressed format, an encrypted format, a fragmentedformat, a packaged format, etc. Machine readable instructions asdescribed herein may be stored as data (e.g., portions of instructions,code, representations of code, etc.) that may be utilized to create,manufacture, and/or produce machine executable instructions. Forexample, the machine readable instructions may be fragmented and storedon one or more storage devices and/or computing devices (e.g., servers).The machine readable instructions may require one or more ofinstallation, modification, adaptation, updating, combining,supplementing, configuring, decryption, decompression, unpacking,distribution, reassignment, etc. in order to make them directly readableand/or executable by a computing device and/or other machine. Forexample, the machine readable instructions may be stored in multipleparts, which are individually compressed, encrypted, and stored onseparate computing devices, wherein the parts when decrypted,decompressed, and combined form a set of executable instructions thatimplement a program such as that described herein. In another example,the machine readable instructions may be stored in a state in which theymay be read by a computer, but require addition of a library (e.g., adynamic link library (DLL)), a software development kit (SDK), anapplication programming interface (API), etc. in order to execute theinstructions on a particular computing device or other device. Inanother example, the machine readable instructions may need to beconfigured (e.g., settings stored, data input, network addressesrecorded, etc.) before the machine readable instructions and/or thecorresponding program(s) can be executed in whole or in part. Thus, thedisclosed machine readable instructions and/or corresponding program(s)are intended to encompass such machine readable instructions and/orprogram(s) regardless of the particular format or state of the machinereadable instructions and/or program(s) when stored or otherwise at restor in transit.

In some examples disclosed herein, a hardware processor (e.g., thecontroller 318, the controller 1028, and/or the controller 1126) may beused to execute the instructions of FIG. 12 to implement the examplecompensation network 302 of FIG. 3, the example compensation network1001 of FIG. 10, and/or the example compensation network 1101 of FIG.11. The hardware processor can be, for example, a server, an electroniccontrol unit (ECU) of a vehicle, a personal computer, a workstation, orany other type of computing device. The hardware processor may be asemiconductor based (e.g., silicon based) device. For example, thehardware processor may obtain a measurement (e.g., a currentmeasurement, a voltage measurement, etc.) associated with the boostconverter system 300, the buck converter system 1000, and/or thebuck-boost converter system 1100, and/or generate a control signal thatis to be obtained by the ZVS switch 324, the ZVS switch 1020, and/or theenable switch 1118. In such examples, the hardware processor cangenerate a control signal that is to be obtained by the ZVS switch 324,the ZVS switch 1020, and/or the enable switch 1118 to provide current orremove current from the inductor 304 of FIG. 3, the inductor 1010 ofFIG. 10, and/or the inductor 1110 of FIG. 11. For example, the hardwareprocessor may direct and/or otherwise cause the compensation network302, the compensation network 1001, and/or the compensation network 1101to turn off the ZVS switch 324, the ZVS switch 1020, and/or the enableswitch 1118 in response to an indication of voltage in the boostconverter system 300, the buck converter system 1000, and/or thebuck-boost converter system 1100.

As mentioned above, the example processes of FIG. 12 may be implementedusing executable instructions (e.g., computer and/or machine readableinstructions) stored on a non-transitory computer and/or machinereadable medium such as a hard disk drive, a flash memory, a read-onlymemory, a compact disk, a digital versatile disk, a cache, arandom-access memory and/or any other storage device or storage disk inwhich information is stored for any duration (e.g., for extended timeperiods, permanently, for brief instances, for temporarily buffering,and/or for caching of the information). As used herein, the termnon-transitory computer readable medium is expressly defined to includeany type of computer readable storage device and/or storage disk and toexclude propagating signals and to exclude transmission media.

“Including” and “comprising” (and all forms and tenses thereof) are usedherein to be open ended terms. Thus, whenever a claim employs any formof “include” or “comprise” (e.g., comprises, includes, comprising,including, having, etc.) as a preamble or within a claim recitation ofany kind, it is to be understood that additional elements, terms, etc.may be present without falling outside the scope of the correspondingclaim or recitation. As used herein, when the phrase “at least” is usedas the transition term in, for example, a preamble of a claim, it isopen-ended in the same manner as the term “comprising” and “including”are open ended. The term “and/or” when used, for example, in a form suchas A, B, and/or C refers to any combination or subset of A, B, C such as(1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) Bwith C, and (7) A with B and with C. As used herein in the context ofdescribing structures, components, items, objects and/or things, thephrase “at least one of A and B” is intended to refer to implementationsincluding any of (1) at least one A, (2) at least one B, and (3) atleast one A and at least one B. Similarly, as used herein in the contextof describing structures, components, items, objects and/or things, thephrase “at least one of A or B” is intended to refer to implementationsincluding any of (1) at least one A, (2) at least one B, and (3) atleast one A and at least one B. As used herein in the context ofdescribing the performance or execution of processes, instructions,actions, activities and/or steps, the phrase “at least one of A and B”is intended to refer to implementations including any of (1) at leastone A, (2) at least one B, and (3) at least one A and at least one B.Similarly, as used herein in the context of describing the performanceor execution of processes, instructions, actions, activities and/orsteps, the phrase “at least one of A or B” is intended to refer toimplementations including any of (1) at least one A, (2) at least one B,and (3) at least one A and at least one B.

FIG. 12 is a flowchart representative of a process 1200 that may beimplemented using logic or machine readable instructions that may beexecuted to implement the compensation network 302 of FIG. 3, thecompensation network 1001 of FIG. 10, or the compensation network 1101of FIG. 11, to reduce switching losses occurring in the boost convertersystem 300, the buck converter system 1000, or the buck-boost convertersystem 1100, respectively. In the example illustrated in FIG. 12, acomparator (e.g., the comparator 320, the comparator 1016, or thecomparator 1114) obtains a first voltage signal (e.g., the input voltagesignal (line 327), the input voltage signal (line 1015), or the inputvoltage signal (line 1115)) (block 1210). Additionally, the comparator(e.g., the comparator 320, the comparator 1016, or the comparator 1114)obtains a second voltage signal (e.g., the output voltage signal (line311), the output voltage signal (line 1011), or the output voltagesignal (line 1111)) (block 1220).

In response, the comparator (e.g., the comparator 320, the comparator1016, or the comparator 1114) determines whether the first voltagesignal (e.g., the input voltage signal (line 327), the input voltagesignal (line 1015), or the input voltage signal (line 1115)) and thesecond voltage signal (e.g., the output voltage signal (line 311), theoutput voltage signal (line 1011), or the output voltage signal (line1111)) are a threshold difference from each other (block 1230). Forexample, the threshold difference may be whether the voltage of theinput voltage signal (e.g., the input voltage signal (line 327)) is halfthe magnitude of the second voltage signal (e.g., the output voltagesignal (line 311)). If the control of block 1230 returns a NO, thencontrol proceeds to block 1260. The control of block 1260 is explainedin further detail below.

Alternatively, if the control of block 1230 returns a YES, then a logicgate (e.g., the logic gate 322, the logic gate 1018, or the logic gate1116) determines whether peak response signal (e.g., the peak thresholdsignal (line 329), the peak threshold signal (line 1027), or the peakthreshold signal (line 1127)) is generated (block 1240). In response thecontrol of block 1240 returning a NO, then control returns to block1230.

Alternatively, in response the control of block 1240 returning a YES,then the logic gate (e.g., the logic gate 322, the logic gate 1018, orthe logic gate 1116) generates an example enable signal (e.g., thetrigger signal (line 319), the trigger signal (line 1019), or thetrigger signal (line 1119)) (block 1250). In examples disclosed herein,control proceeds to block 1260 in which the compensating network (e.g.,the compensation network 302, the compensation network 1001, or thecompensation network 1101) determines whether to continue operating(block 1260).

If the compensating network (e.g., the compensation network 302, thecompensation network 1001, or the compensation network 1101) determinesto continue operating, then control returns to block 1210.Alternatively, if the compensating network (e.g., the compensationnetwork 302, the compensation network 1001, or the compensation network1101) determines not to continue operating, then the process stops. Inexamples disclosed herein, any of a loss of power, damaged, device,shutoff signal, etc., may provoke and/or otherwise cause control tostop.

From the foregoing, it will be appreciated that example methods,apparatus and articles of manufacture have been disclosed that reducesresidual switching losses present in power converter systems by enablingsoft switching under all operating conditions. The disclosed methods,apparatus and articles of manufacture improve the efficiency of using acomputing device by providing a negative current to an inductor of apower converter system, thereby allowing a respective switching deviceto be enabled with zero, or substantially little, voltage across theswitching device. The disclosed methods, apparatus and articles ofmanufacture are accordingly directed to one or more improvement(s) inthe functioning of a computer.

Although certain example methods, apparatus and articles of manufacturehave been disclosed herein, the scope of coverage of this patent is notlimited thereto. On the contrary, this patent covers all methods,apparatus and articles of manufacture fairly falling within the scope ofthe claims of this patent.

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 8. A circuit to reduce switching loss in aconverter having an input voltage node, an output voltage node, aninductor coupled between the input voltage node and the output voltagenode, a switch node between the inductor and the output voltage node anda first transistor coupled between the switch node and ground, thecircuit comprising: a controller coupled to a control terminal of thefirst transistor; and a compensation network including: an amplifierhaving an output, a first input directly coupled to the input voltagenode and a second input directly coupled through a resistive divider tothe output voltage node; a logic gate having an output, a first inputcoupled to the controller and a second input directly coupled to theoutput of the amplifier; and a second transistor having a controlterminal directly coupled to the output of the logic gate, a firstcurrent terminal coupled to the switch node and a second currentterminal coupled to the output voltage node.
 9. The apparatus of claim8, wherein the compensation is adapted to conduct a current to theconverter in response to a first voltage at the input voltage node beinga threshold difference than a second voltage at the output voltage node.10. The apparatus of claim 9, wherein the controller is configured togenerate an enable signal to enable the second transistor in response toa third voltage at a switch node in the converter being a peakthreshold.
 11. The apparatus of claim 9, wherein the thresholddifference is satisfied when the first voltage is less than half of thesecond voltage.
 12. The apparatus of claim 9, wherein the compensationnetwork is adapted to conduct the current in parallel with a rectifyingdevice in the converter.
 13. The apparatus of claim 9, wherein thecurrent is adapted to conduct through the second transistor, wherein thesecond transistor is smaller than the first transistor, and whereincurrent conducts through the second transistor when a first voltage at afirst current terminal of the second transistor is equivalent to asecond voltage at a second current terminal of the second transistor.14. The apparatus of claim 8, wherein the converter is a boostconverter.
 15. A system comprising: a converter including a firsttransistor, an input node, an output node, and a switch node; acontroller coupled to a control terminal of the first transistor anddirectly coupled to the input node, the output node and the switch node;and a compensation network including a second transistor, thecompensation network is directly coupled to the input node, to theoutput node, and to the controller, and wherein the second transistor iscoupled to the switch node and to the output node.
 16. The system ofclaim 15, wherein the second transistor is configured to conduct acurrent in response to a first voltage at the input node being athreshold difference from a second voltage at the output node.
 17. Thesystem of claim 16, wherein the threshold difference is satisfied whenthe first voltage is less than half of the second voltage.
 18. Thesystem of claim 15, wherein the second transistor is adapted to conducta current when a first voltage the switch node is equivalent to a secondvoltage at the output node.
 19. The system of claim 15, wherein thesecond transistor is smaller than the first switch.
 20. The system ofclaim 15, wherein the converter is a boost converter.
 21. A converterfor converting an input voltage at an input node to an output voltage atan output node, the converter having an inductor coupled between theinput node and a switching node and the converter comprising: a firsttransistor coupled between the switching node and ground; a diode havingan anode coupled to the switching node and a cathode coupled to theoutput node; a zero-voltage switching (ZVS) controller coupled to theinput node, the switching node and the output node, the controllerhaving an output coupled to a control terminal of the first transistor;a compensation network directly coupled to the input node and the outputnode through a resistive divider and having a ZVS switch with a firstcurrent terminal coupled to the anode of the diode and a second currentterminal coupled to the cathode of the diode; and wherein the ZVS switchis adapted to conduct current from the from the second current terminalto the first current terminal.